JPS6240836U - - Google Patents
Info
- Publication number
- JPS6240836U JPS6240836U JP13189485U JP13189485U JPS6240836U JP S6240836 U JPS6240836 U JP S6240836U JP 13189485 U JP13189485 U JP 13189485U JP 13189485 U JP13189485 U JP 13189485U JP S6240836 U JPS6240836 U JP S6240836U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- gates
- internal wiring
- wire bonding
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13189485U JPS6240836U (en]) | 1985-08-28 | 1985-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13189485U JPS6240836U (en]) | 1985-08-28 | 1985-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6240836U true JPS6240836U (en]) | 1987-03-11 |
Family
ID=31030767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13189485U Pending JPS6240836U (en]) | 1985-08-28 | 1985-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6240836U (en]) |
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1985
- 1985-08-28 JP JP13189485U patent/JPS6240836U/ja active Pending